One of the challenges facing processor designers is the handling of a number of communications between processors, particularly over interconnect systems having circuitry comprising switches and links for directing messages around arrays or large arrangements of processors, for example arranged on the same circuit board or chip.
A particular difficulty is in communicating control information. Messages sent over such an interconnect are typically made up of discrete bytes of data. However, there must also be a mechanism for transmitting control information for controlling the interconnect itself. The control information could be for example an “end-of-message” signal to close a channel established by the switches or a request to read or write to a control register of one of the switches or links. Finding a control mechanism which conveniently co-inhabits with the data transmission mechanism can be problematic.
Taking the “end-of-message” example as an illustration of this problem, a circuit designer might typically assign the byte-value 255 within a message as a control value to signal the end of a message and thus cause the switches to close the channel between two communicating processors. However, if a software developer wanted to communicate the actual number 255 to the destination software, without this being misinterpreted as a request to close the channel, then a complicated escape sequence would conventionally have to be built into the transfer mechanism in order to prevent the interconnect from being triggered in this way when desired.
Furthermore, there is a need to provide a more flexible control mechanism which is useful over a range of different application specific needs.